Generally, one of the driving factors in the design of modern electronics is the amount of computing power and storage that can be shoehorned into a given space. One method used to pack more computing power into a given space and reduce the distance between various chips forming a system is to stack chips, with interconnects running vertically. Embedded interconnects, or metal filled vias in a substrate, are commonly called through silicon vias (“TSVs”). TSVs can be used to connect chips on opposite sides of a substrate, or provide chip level connections through the body of the chip.
TSVs are also used to create 3D integrated circuits, and are advantageous over wire bonding or other connection techniques because the density of the vias is substantially higher, and because the length of the connections is shorter. A 3D package such as System in Package, Chip Stack Multi-Chip Module (MCM), etc. contains two or more chips (integrated circuits) stacked vertically so that they occupy less space and/or have greater connectivity. An alternate type of 3D package is Silicon Carrier Packaging Technology, where ICs are not stacked but a carrier substrate containing TSVs is used to connect multiple ICs together in a package. In most 3D packages, the stacked chips are wired together along their edges and this edge wiring slightly increases the length and width of the package and usually requires an interposer layer between the chips. In some 3D packages, through-silicon vias replace edge wiring by creating vertical connections through the body of the chips. The resulting package has no added length or width. Because no interposer is required, a TSV 3D package can also be flatter than an edge-wired 3D package. This TSV technique is sometimes also referred to as TSS (Through-Silicon Stacking or Thru-Silicon Stacking.) A 3D integrated circuit (3D IC) is a single integrated circuit built by stacking silicon wafers and/or dies and interconnecting them vertically so that they behave as a single device. By using TSV technology, 3D ICs can pack a great deal of functionality into a small footprint. The different dies in the stack may be heterogeneous, e.g. combining CMOS logic, DRAM and III-V materials into a single IC.
The use of silicon as an interposer or substrate is not required, even though the term refers to the vias being in silicon. These interposer substrates are commonly silicon, glass or some other insulator, with copper, gold or other conductors disposed in the vias through the interposer.